1. Field of the Invention
The present invention relates to an expansion system suitable for expanding, e.g., a cache memory system.
2. Description of the Related Art
Along with the rapid development of LSI techniques, a high-performance cache memory LSIs (to be referred to as cache LSIs hereinafter) which are integrated at high density and have high operation speed are available. Of these cache LSIs, one or both of a cache directory portion and a cache data portion are realized by LSIs. The capacity of a normal cache memory system varies depending on the scale or performance of a computer system. Therefore, a cache memory system is constituted by a necessary number of cache LSIs. Each cache LSI has a chip select terminal. A cache LSI which receives a chip select signal at its chip select terminal is accessed by a microprocessor (.mu. processor) The chip select signal is generated by a decoder externally attached to the cache memory system. More specifically, as shown in FIG. 1, .mu. processor 11 is connected to address decoder 13 through address bus 17. .mu. processor 11 is also connected to cache LSIs 15a, 15b, 15c, and 15d through address bus 17, data bus 19, and control bus 21. An address for accessing one of cache LSIs output from .mu. processor 11 is supplied to address decoder 13. Address decoder 13 decodes this address, and enables one of a plurality of chip select signal lines 23. As a result, .mu. processor 11 performs a read/write access with respect to the cache LSI to which the enable chip select signal is supplied. A case wherein a system is expanded using a plurality of identical chips in this manner is described in, e.g., "The McGraw-Hill Computer Handbook" (1983), subtitle "7-6 Connecting Memory Chips to A Computer Bus" pp. 7-16 through 7-21.
In this manner, when a memory system is expanded using a plurality of cache LSIs, address decoder 13 and a plurality of chip select signal lines 23 must be arranged. For this reason, the hardware scale is increased, and disturbs integration of a system LSI. A signal delay occurs due to address decoder 13 and chip select signal lines 23. For this reason, a signal delay amount of a cache LSI when a single cache LSI is used is different from that when a plurality of cache LSIs are used, and it is disadvantageous for performance of the system.